Company : LSI India Research & Development Pvt Ltd
Website : www.lsi.com
Education : M.Tech & B.E/ B.Tech
Experience : 0 – 1 Years
Location : Bangalore
Website : www.lsi.com
Education : M.Tech & B.E/ B.Tech
Experience : 0 – 1 Years
Location : Bangalore
Designation : ASIC DvDs Engineer 1
Industry Type : Semiconductors / Electronics
Role : Software Developer
Functional Area : IT Software – Embedded, EDA, VLSI, ASIC, Chip Design
Role : Software Developer
Functional Area : IT Software – Embedded, EDA, VLSI, ASIC, Chip Design
Job Description :
Job profile:
Participate in all the different phases of Physical design implementation of SoCs.
Participate in Block level Physical design of complex Chip/IPs.
Participate in STA and timing closure activities
Work with chip integration team closely in Timing closure
Complete the Block level/SoC Design including the physical design verification
Participate in chip level floor planning and hierarchical design
Participate in all the different phases of Physical design implementation of SoCs.
Participate in Block level Physical design of complex Chip/IPs.
Participate in STA and timing closure activities
Work with chip integration team closely in Timing closure
Complete the Block level/SoC Design including the physical design verification
Participate in chip level floor planning and hierarchical design
Required skills:
Hands-on experience with back-end tools (floorplaning and place & route) preferably using ICC/Astro
Clock tree synthesis
Back-end design flows from Synthesis to physical design verification including various scan and BIST methodologies
Static timing analysis and timing closure
Physical design verification ( LVS, DRC)
Power analysis preferably with voltage storm/Cooltime
Chip finishing flow
Hands-on experience with back-end tools (floorplaning and place & route) preferably using ICC/Astro
Clock tree synthesis
Back-end design flows from Synthesis to physical design verification including various scan and BIST methodologies
Static timing analysis and timing closure
Physical design verification ( LVS, DRC)
Power analysis preferably with voltage storm/Cooltime
Chip finishing flow
As part of Design Implementation team, you will be responsible for all aspects of physical design implementation from Netlist to GDSII. Applicant will also be involved in chip floor planing, power analysis, full chip integration, timing closure, and physical verification (DRC/LVS/ERC/Antenna), tape out and mask review.
Applicant will also participate in establishing and defining implementation methodologies and flow automation. Experience should be focused on design implementation.
Applicant will also participate in establishing and defining implementation methodologies and flow automation. Experience should be focused on design implementation.
Imagine your future. Accelerated.
Desired Profile :
M.Tech & B.E/ B.Tech from a reputed institute with good academic record specialization in EE, Computer Science Engineering
Experience: 0-1 years of experience and should have executed P & R for large chip designs
Experience in physical design of SoCs.
Candidate must have relevant experience
Experience in physical design of SoCs.
Candidate must have relevant experience
0 comments :
Post a Comment